The present invention relates to a semiconductor device, and more particularly to a composite circuit which is a combination of a MOS (metal-oxide-semiconductor) transistor and a bipolar transistor, or a MOS-drive bipolar-output logic circuit.
Various composite circuits which utilize a low power consumption of CMOS transistors and a high load drive capability of bipolar transistors have been known.
One of those, which is shown in FIG. 1, is a circuit similar to one shown in FIG. 8 of the IEEE Transaction on Electron Devices, Vol. ED-16, No. 11, Nov. 1969, page 950. In FIG. 1, numeral 1 denotes a PMOS transistor having a source thereof connected to a power supply +V, a gate thereof connected to an input terminal IN and a drain thereof connected to a base of an NPN transistor 3, and numeral 2 denotes an NMOS transistor having a drain thereof connected to an output terminal OUT, a gate thereof connected to the input terminal IN and a source thereof connected to a base of an NPN transistor 4. A collector of the NPN transistor 3 is connected to the power supply +V and an emitter thereof is connected to the output terminal OUT. A collector of the NPN transistor 4 is connected to the output terminal OUT and an emitter thereof is connected to a common potential point or a ground potential point GND.
The operation of the circuit is as follows. When the input terminal IN is at an "L" level, the NMOS transistor 2 is off and the NPN transistor 4 is also off. On the other hand, the PMOS transistor 1 is on and a base current is supplied to the NPN transistor 3 through the PMOS transistor 1. As a result, a charge current flows from the NPN transistor 3 to a load (not shown) and the output terminal OUT is switched to an "H" level. When the input terminal IN is at the "H" level, the PMOS transistor 1 is off and the NPN transistor 3 is also off. On the other hand, the NMOS transistor 2 is on and a base current is supplied to the NPN transistor 4 through the NMOS transistor 2 and the NPN transistor 4 is turned on. As a result, the charge stored in the load is discharged through the NPN transistor 4 and the output terminal OUT is switched to the "L" level. In this circuit, an output voltage level of the circuit is shifted by base-emitter voltages V.sub.BEQl and V.sub. BEQ2 of the NPN transistors 3 and 4. Thus, the "H" level is (+V-V.sub.VSEQl) and the "L" level is V.sub.BEQ2.
FIG. 2 shows a circuit similar to one disclosed in Japanese Patent Unexamined Publication No. 54-148469. In FIG. 2, numeral 5 denotes PMOS transistor having a source thereof connected to a power supply +V, a gate thereof connected to an input terminal IN and a drain thereof connected to a junction point or node B of a base of an NPN transistor 7 and a base of a PNP transistor 8. Numeral 6 denotes an NMOS transistor having a drain thereof connected to said junction point, a gate thereof connected to the input terminal IN and a source thereof connected to a power supply -V. A collector of the NPN transistor 7 is connected to the power supply +V and an emitter thereof is connected to an output terminal OUT. An emitter of the PNP transistor 8 is connected to the output terminal OUT and a collector thereof is connected to the power supply -V.
In this circuit, an output voltage level is also shifted by base-emitter voltages V.sub.BEQl and V.sub.BEQ2 of the NPN transistor 7 and the PNP transistor 8. Thus, the "H" level is (+V-V.sub.BEQl) and the "L" level is (-V+V.sub.BEQ2).
FIG. 3 shows a circuit similar to one disclosed in Japanese Unexamined Patent Application No. 52-26181. In FIG. 3, numeral 9 denotes a PMOS transistor having a source thereof connected to a power supply +V, a gate thereof connected to an input terminal IN and a drain thereof connected to a base of an NPN transistor 11. Numeral 10 denotes an NMOS transistor having a drain thereof connected to an output terminal OUT, a gate thereof connected to an input terminal IN and a source thereof connected to a power supply -V. A collector of the NPN transistor 11 is connected to the power supply +V and an emitter thereof is connected to the output terminal OUT.
In this circuit, an output voltage level is also shifted by base-emitter voltage V.sub.BEQl of the NPN transistor 11. Thus, the "H" level is (+V-V.sub.BEQl) and the "L" level is -V.
In FIG. 4, numeral 12 denotes a symbol of a MOS-drive bipolar-output logic circuit having offsets at the output levels shown in FIGS. 1 to 3.
FIG. 5 shows a MOS-drive bipolar-output tri-state circuit 13 which is similar to the circuit of FIG. 20 disclosed in U.S. patent application Ser. No. 703,171 entitled "Arithmetic Operation Unit and Arithmetic Operation Circuit" filed Feb. 19, 1985 in the name of Hitachi, Ltd., based on Japanese Patent Applications Nos. 59-31257 filed on Feb. 20, 1984 and 60-2020 filed on Jan. 11, 1985. In the figure, numerals 14 and 15 denote series-connected PMOS transistors, a source of the PMOS 14 is connected to a power supply +V and a gate thereof is connected to an input terminal E. A gate of the PMOS transistor 15 is connected to an input terminal IN and a drain thereof is connected to a base of a NPN transistor 18. Numerals 16 and 17 denote series-connected NMOS transistors. A drain of the NMOS transistor 16 is connected to an output terminal OUT and a gate thereof is connected to the input terminal IN. A gate of the NMOS transistor 17 is connected to an input terminal E and a source thereof is connected to a base of an NPN transistor 19. A collector of the NPN transistor 18 is connected to the power supply +V and an emitter thereof is connected to the output terminal OUT. A collector of the NPN transistor 19 is connected to the output terminal OUT and an emitter thereof is connected to a ground GND, a load capacitor C.sub.L is connected to the output terminal OUT.
This circuit is a tri-state logic circuit and the output level is shifted. The operation is as follows.
When the input terminal E is at the "L" level and the input terminal E is at the "H" level, the PMOS transistor 14 and the NMOS transistor 17 are off, and the NPN transistor 18 and the NPN transistor 19 are also off. As a result, the output terminal OUT is in a high impedance state regardless of the level of the input terminal IN.
When the input terminal E is at the "H" level and the input level E is at the "L" level, the NMOS transistor 17 and the PMOS transistor 14 are on. If the input terminal IN is at the "L" level, the PMOS transistor 15 and the NPN transistor 18 are on and the output terminal OUT is charged to (+V-V.sub.BEQl). If the input terminal IN is at the "H" level, the NMOS transistor 16 and the NPN transistor 19 are on and the output terminal OUT is discharged to +V.sub.BEQ2. Thus, this circuit functions as an inverter having an output "H" level thereof shifted down by V.sub.BEQl and an output "L" level thereof shifted up by V.sub.BEQ2.
In FIG. 6, numeral 20 denotes a symbol of the circuit of FIG. 5.
The MOS-bipolar composite circuits described above are different from a CMOS transistor buffer circuit in that they can switch a large capacitive load at a high speed and the output voltage level is shifted by the base-emitter voltage V.sub.BE of the bipolar transistor.
However, when such an output voltage level shifted signal is used as a gate drive signal of a MOS switch, the MOS switch may not be completely turned off in a certain circuit. A typical MOS switch circuit in which such a problem may arise is a well-known clocked inverter shown in FIG. 7. A numeral 21 in FIG. 8 denotes a symbol of FIG. 7.
In FIG. 7, numeral 22 denotes a PMOS transistor having a source thereof connected to a power supply +V, a gate thereof connected to an input terminal IN and a drain thereof connected to a source of a PMOS transistor 23. A gate of the PMOS transistor 23 is connected to a clock terminal .phi. and a drain thereof is connected to an output terminal OUT. Numeral 24 denotes an NMOS transistor having a drain thereof connected to the output terminal OUT, a gate thereof connected to a clock terminal .phi. and a source thereof connected to a drain of an NMOS transistor 25. A gate of the NMOS transistor 25 is connected to the input terminal IN and a source thereof is connected to a common potential point GND, C.sub.s denotes a stray capacitance at the output terminal OUT.
The operation of this circuit is as follows. When .phi. is at the "H" level and .phi. is at the "L" level, the PMOS transistor 23 and the NMOS transistor 24 are on. If the input terminal IN is at the "L" level, the NMOS transistor 25 is off and the PMOS transistor 22 is on, and the stray capacitance CS is charged through the PMOS transistors 22 and 23 so that the output terminal OUT assumes the "H" level. On the other hand, if the input terminal IN is at the "H" level, the PMOS transistor 22 is off and the NMOS transistor 25 is on, and the charge stored in the stray capacitor C.sub.s is discharged through the NMOS transistors 24 and 25 so that the output terminal OUT assumes the "L" level.
When .phi. is at the "L" level and .phi. is at the "H" level, the PMOS transistor 23 and the NMOS transistor 24 are off. Thus, the level of the output terminal is held irrespective of the level of the input terminal IN. Thus, this circuit has a dynamic latch function.
However, when the clocks .phi. and .phi. are supplied from the prior art composite circuit shown in FIGS. 1 to 3 or the composite circuit shown in FIG. 5 which is not prior art, the operation in the hold state is as follows. Let us assume that the power supply +V is 5 volts, the "H" levels of .phi. and .phi. are 4.3 volts, the "L" levels thereof are 0.7 volt, the "H" level of the input terminal IN is 5 volts and the "L" level thereof is 0 volt.
When .phi.=0.7 volt, .phi.=4.3 volt and the output terminal OUT is held at the "H" level, the PMOS transistor 23 and the NMOS transistor 24 conduct slightly because the gate-source voltages thereof are not completely zero. If the input terminal IN is at the "L" level, the NMOS transistor 25 is off and the PMOS transistor 22 is on. Therefore, the output terminal OUT is held at the "H" level. If the input terminal IN is at the "H" level, the NMOS transistor 25 is on and the charge stored in the stray capacitor C.sub.S is discharged through the slightly conducting NMOS transistor 24 and the on NMOS transistor 25. As a result, the output terminal OUT is switched from the "H" level to the "L" level. Similarly, when the output terminal OUT is held at the "L" level and the input terminal IN is at the "L" level, the NMOS transistor 25 is off and the PMOS transistor 22 is on. As a result, the charge stored in the stray capacitor C.sub.S is charged through the PMOS transistor 22 which is now in on state and the slightly conducting PMOS transistor 23 so that the output terminal OUT is switched from the "L" level to the "H" level.
Thus, in the prior art composite circuits, the output terminal OUT is not completely "L" level, that is, the level of the output terminal OUT does not completely reach the common potential or the lower potential of the power supply when the output terminal OUT is at the "L" level, and the output terminal OUT is not completely "H" level, that is, the level of the output terminal does not reach the higher potential of the power supply when the output terminal OUT is at the "H" level. This adversely affects to the succeeding stage circuit.
In a circuit shown in Japan Patent Unexamined Publication No. 59-205828 (FIG. 4 in particular), a logic circuit which is a composite circuit comprising MOS transistors and bipolar transistor and another logic circuit comprising MOS transistors and having the same function as the first logic circuit are connected in parallel so that the output signal level completely reach the "L" or "H" level. In this circuit, since an input capacitance is larger than that of a logic circuit which comprises only the composite circuit, an operation speed of a preceding circuit to drive the logic circuit is lower and hence an overall speed is reduced. Furthermore, in a multi-input buffer circuit, the number of elements required for the parallel MOS logic circuit increases in proportion to the number of inputs.
Reference may be made to U.S. patent application No. 680,495 filed Dec. 11, 1984 in the name of Hitachi, Ltd., and to Japanese Patent Unexamined Publication No. 59-205828.